In multi-signal data transfer, for example, multi-wire differential signaling such as 3-phase or N-factorial low-voltage differential signaling (LVDS), transcoding (e.g., the digital-to-digital data conversion of one encoding to another) may be done to embed symbol clock information by causing a symbol transition at every symbol cycle, instead of sending clock information in separate data lanes (transmission paths). Embedding clock information by such transcoding is an effective way to minimize skew between clock and data signals, as well as to eliminate the necessity of a phase-locked loop (PLL) to recover the clock information from the data signals.
Some transcoding solutions (e.g., 3-wire differential signaling and/or 3-phase signaling) have implemented embedded clock information, but lack scalability.
Therefore, an efficient transcoding method is needed that supports any number of wires used in multi-wire signaling, such as N factorial differential signaling, and any number of symbols in a group that to be transcoded from any binary number.